229 search results - page 34 / 46 » Fault-Tolerant Clock Synchronization in CAN |
CHES
2004
Springer
14 years 1 months ago
2004
Springer
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
ENTCS
2006
13 years 7 months ago
2006
Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to ...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
SIGMETRICS
2010
ACM
14 years 15 days ago
2010
ACM
We show that CSMA is able to spontaneously synchronize transmissions in a wireless network with constant-size packets, and that this property can be used to devise efficient synch...