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ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
14 years 8 days ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain
CF
2010
ACM
14 years 1 months ago
Load balancing using dynamic cache allocation
Supercomputers need a huge budget to be built and maintained. To maximize the usage of their resources, application developers spend time to optimize the code of the parallel appl...
Miquel Moretó, Francisco J. Cazorla, Rizos ...
PPOPP
2009
ACM
14 years 8 months ago
Effective performance measurement and analysis of multithreaded applications
Understanding why the performance of a multithreaded program does not improve linearly with the number of cores in a sharedmemory node populated with one or more multicore process...
Nathan R. Tallent, John M. Mellor-Crummey
ARC
2007
Springer
150views Hardware» more  ARC 2007»
14 years 4 days ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
ICS
2001
Tsinghua U.
14 years 18 days ago
Reducing the complexity of the issue logic
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
Ramon Canal, Antonio González