475 search results - page 26 / 95 » Feasible distributed CSP models for scheduling problems |
HIPC
2005
Springer
14 years 1 months ago
2005
Springer
We examine the problem of scheduling concurrent independent flows on multiple-disk I/O storage systems. Two models are considered: in the shared buffer model the memory buffer is ...
DFVLR
1987
13 years 11 months ago
1987
: This paper examines the argument for dataflow architectures in "Two Fundamental Issues in Multiprocessing[5]." We observe two key problems. First, the justification of ...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Schedule synthesis based on reachability analysis of timed automata has received attention in the last few years. The main strength of this approach is that the expressiveness ...
LCTRTS
2001
Springer
13 years 12 months ago
2001
Springer
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
RTSS
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper, we address the problem of symbolically computing the region in the parameter’s space that guarantees a feasible schedule, given a set of real-time tasks character...