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APCSAC
2004
IEEE
13 years 11 months ago
A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
Xiaobin Li, Jean-Luc Gaudiot
JSA
2007
123views more  JSA 2007»
13 years 7 months ago
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Ch...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
ICC
2000
IEEE
123views Communications» more  ICC 2000»
14 years 1 days ago
A Per-Flow Based Node Architecture for Integrated Services Packet Networks
As the Internet transforms from the traditional best-effort service network into QoS-capable multi-service network, it is essential to have new architectural design and appropriate...
Dapeng Wu, Yiwei Thomas Hou, Takeo Hamada, Zhi-Li ...
DATE
2006
IEEE
66views Hardware» more  DATE 2006»
14 years 1 months ago
Power/performance hardware optimization for synchronization intensive applications in MPSoCs
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
SBCCI
2003
ACM
96views VLSI» more  SBCCI 2003»
14 years 26 days ago
SoCIN: A Parametric and Scalable Network-on-Chip
Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip (SoCs) meet the major communication requirements of these systems, of...
Cesar Albenes Zeferino, Altamiro Amadeu Susin