Sciweavers

163 search results - page 13 / 33
» Features of Future Network Processor Architectures
Sort
View
IEEEPACT
2008
IEEE
14 years 2 months ago
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
Katherine E. Coons, Behnam Robatmili, Matthew E. T...
TC
2011
13 years 2 months ago
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
ANCS
2008
ACM
13 years 9 months ago
A programmable architecture for scalable and real-time network traffic measurements
Accurate and real-time traffic measurement is becoming increasingly critical for large variety of applications including accounting, bandwidth provisioning and security analysis. ...
Faisal Khan, Lihua Yuan, Chen-Nee Chuah, Soheil Gh...
HPCA
2009
IEEE
14 years 8 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
22
Voted
ECOOP
2008
Springer
13 years 9 months ago
Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary
Abstract. The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores ar...
Shan Shan Huang, Amir Hormati, David F. Bacon, Rod...