Sciweavers

163 search results - page 9 / 33
» Features of Future Network Processor Architectures
Sort
View
ERSA
2009
146views Hardware» more  ERSA 2009»
13 years 5 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...
DSD
2008
IEEE
139views Hardware» more  DSD 2008»
13 years 9 months ago
Revisiting the Cache Effect on Multicore Multithreaded Network Processors
Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new ...
Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. ...
ICDCSW
2003
IEEE
14 years 27 days ago
A Flexible Web Service Based Architecture for Wireless Sensor Networks
The current sensor networks are assumed to be designed for specific applications, having strongly coupled data communication protocols. The future sensor networks are envisioned a...
Flávia Coimbra Delicato, Paulo F. Pires, Lu...
CASES
2006
ACM
13 years 11 months ago
High-performance packet classification algorithm for many-core and multithreaded network processor
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang
CF
2004
ACM
14 years 1 months ago
A first glance at Kilo-instruction based multiprocessors
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
Marco Galluzzi, Valentin Puente, Adrián Cri...