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IPPS
2010
IEEE
13 years 5 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
RTAS
2005
IEEE
14 years 1 months ago
Improving WCET by Optimizing Worst-Case Paths
It is advantageous to perform compiler optimizations to lower the WCET of a task since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compi...
Wankang Zhao, William C. Kreahling, David B. Whall...
CASES
2004
ACM
14 years 27 days ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder
CCE
2004
13 years 7 months ago
Pharmaceutical supply chains: key issues and strategies for optimisation
Supply chain optimisation is now a major research theme in process operations and management. A great deal of research has been undertaken on facility location and design, invento...
Nilay Shah
ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
13 years 11 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick