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DATE
2007
IEEE
128views Hardware» more  DATE 2007»
14 years 1 months ago
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
HYBRID
2003
Springer
14 years 20 days ago
On the Application of Hybrid Control to CPU Reservations
Abstract. An important class of soft real-time applications require dynamic allocation of computational resources in order to comply with their quality of service (QoS) requirement...
Luigi Palopoli, Luca Abeni, Giuseppe Lipari
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
13 years 11 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...
CGO
2009
IEEE
14 years 2 months ago
Software Pipelined Execution of Stream Programs on GPUs
—The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. This model allows programmers to sp...
Abhishek Udupa, R. Govindarajan, Matthew J. Thazhu...
CORR
2008
Springer
150views Education» more  CORR 2008»
13 years 7 months ago
Enhanced Energy-Aware Feedback Scheduling of Embedded Control Systems
Dynamic voltage scaling (DVS) is one of the most effective techniques for reducing energy consumption in embedded and real-time systems. However, traditional DVS algorithms have in...
Feng Xia, Longhua Ma, Wenhong Zhao, Youxian Sun, J...