172 search results - page 20 / 35 » FinFET-based SRAM design |
FPL
2008
Springer
13 years 9 months ago
2008
Springer
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
INFOCOM
1999
IEEE
13 years 11 months ago
1999
IEEE
One of the key design issues for the new generation IP routers is the route lookup mechanism. For each incoming IP packet, the IP routing requires to perform a longest prefix match...
APCSAC
2004
IEEE
13 years 11 months ago
2004
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...
ASYNC
2003
IEEE
14 years 24 days ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
VTS
1999
IEEE
13 years 11 months ago
1999
IEEE
1 While multichip module technology has been developed for high performance IC applications, the technology is not widely adopted due to economical reasons. One of the reasons that...