104 search results - page 11 / 21 » First-Class Synchronization Barriers |
ASPLOS
1996
ACM
13 years 11 months ago
1996
ACM
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...
EUROPAR
2009
Springer
13 years 11 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper we use Dijkstra’s algorithm as a challenging, hard to parallelize paradigm to test the efficacy of several parallelization techniques in a multicore architecture....
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
SBT is portable library and tool for on-line debugging and performance monitoring of shared-memory parallel programs using the single-program-multiple-data (SPMD) model of paralle...