104 search results - page 13 / 21 » First-Class Synchronization Barriers |
CF
2010
ACM
14 years 19 days ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
JMLC
2000
Springer
13 years 11 months ago
2000
Springer
Most object-oriented languages offer a limited number of invocation semantics. At best, they define a default mode of synchronous invocation, plus some keywords to express addition...
DEXAW
2010
IEEE
13 years 8 months ago
2010
IEEE
The Web has been flooded with highly heterogeneous data sources that freely offer their data to the public. Careful design and compliance to standards is a way to cope with the he...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock sync...