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EUROPAR
2005
Springer
14 years 3 months ago
Improving Instruction Delivery with a Block-Aware ISA
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
Ahmad Zmily, Earl Killian, Christos Kozyrakis
LCTRTS
2009
Springer
14 years 4 months ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
IEEECIT
2007
IEEE
14 years 4 months ago
Indirect Tag Search Mechanism for Instruction Window Energy Reduction
Instruction window is a key component which extracts Instruction Level Parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor pe...
Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
12 years 7 days ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar