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DATE
2004
IEEE
119views Hardware» more  DATE 2004»
14 years 1 months ago
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Designing custom-extensible instructions for Extensible Processors1 is a computationally complex task because of the large design space. The task of automatically matching candida...
Newton Cheung, Sri Parameswaran, Jörg Henkel,...
CSSE
2008
IEEE
14 years 4 months ago
Generation of Executable Representation for Processor Simulation with Dynamic Translation
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
Jiajia Song, HongWei Hao, Claude Helmstetter, Vani...
IPPS
2010
IEEE
13 years 7 months ago
A low cost split-issue technique to improve performance of SMT clustered VLIW processors
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...
Manoj Gupta, Fermín Sánchez, Josep L...
ISPAN
2000
IEEE
14 years 2 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
CASES
2005
ACM
13 years 11 months ago
Micro embedded monitoring for security in application specific instruction-set processors
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs). This is a generalized methodology for inline monitoring insec...
Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad ...