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RTS
2006
129views more  RTS 2006»
13 years 9 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
ISSS
1998
IEEE
117views Hardware» more  ISSS 1998»
14 years 2 months ago
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation
The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-speci c embedded processors. In order to achieve user retargetability,...
Rainer Leupers
SAC
2005
ACM
14 years 3 months ago
A code compression advisory tool for embedded processors
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
Sreejith K. Menon, Priti Shankar
FPGA
2008
ACM
129views FPGA» more  FPGA 2008»
13 years 11 months ago
Efficient ASIP design for configurable processors with fine-grained resource sharing
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
Quang Dinh, Deming Chen, Martin D. F. Wong
ICPP
2009
IEEE
13 years 7 months ago
Thread Merging Schemes for Multithreaded Clustered VLIW Processors
Several multithreading techniques have been proposed to reduce the resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is ...
Manoj Gupta, Fermín Sánchez, Josep L...