444 search results - page 59 / 89 » Flow Level Simulation of Large IP Networks |
ETVC
2008
13 years 9 months ago
2008
s of the LIX Fall Colloquium 2008: Emerging Trends in Visual Computing Frank Nielsen Ecole Polytechnique, Palaiseau, France Sony CSL, Tokyo, Japan Abstract. We list the abstracts o...
JSA
2010
13 years 2 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
SIGCOMM
2009
ACM
14 years 2 months ago
2009
ACM
Many network applications have stringent end-to-end latency requirements, including VoIP and interactive video conferencing, automated trading, and high-performance computing—wh...
TON
2002
13 years 7 months ago
2002
In order to stem the increasing packet loss rates caused by an exponential increase in network traffic, the IETF has been considering the deployment of active queue management tech...