Sciweavers

501 search results - page 81 / 101
» Flow Time Minimization under Energy Constraints
Sort
View
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
14 years 1 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
WSC
2004
13 years 9 months ago
Simulation Experiment for Improving Construction Processes
From the perspective of flow analysis, the more complex the project, the more wastes are prone to build up, due to the increasing number of interfaces between activities. When pro...
Shihyi Wang, Daniel W. Halpin
ICCAD
2008
IEEE
89views Hardware» more  ICCAD 2008»
14 years 4 months ago
Temperature aware task sequencing and voltage scaling
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
Ramkumar Jayaseelan, Tulika Mitra
WADS
1997
Springer
88views Algorithms» more  WADS 1997»
13 years 11 months ago
Finding Cores of Limited Length
In this paper we consider the problem of nding a core of limited length in a tree. A core is a path, which minimizes the sum of the distances to all nodes in the tree. This proble...
Stephen Alstrup, Peter W. Lauridsen, Peer Sommerlu...
DEXA
2010
Springer
182views Database» more  DEXA 2010»
13 years 7 months ago
Minimum Spanning Tree on Spatio-Temporal Networks
Given a spatio-temporal network (ST network) whose edge properties vary with time, a time-sub-interval minimum spanning tree (TSMST) is a collection of distinct minimum spanning t...
Viswanath Gunturi, Shashi Shekhar, Arnab Bhattacha...