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» Formal Analysis of Processor Timing Models
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ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 8 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
UML
2004
Springer
14 years 1 months ago
SoftContract: Model-Based Design of Error-Checking Code and Property Monitors
This paper discusses a model-based design flow for requirements in distributed embedded software development. Such requirements are specified using a language similar to Linear T...
Luciano Lavagno, Marco Di Natale, Alberto Ferrari,...
VLSID
2008
IEEE
191views VLSI» more  VLSID 2008»
14 years 2 months ago
Programming and Performance Modelling of Automotive ECU Networks
The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementa...
Samarjit Chakraborty, Sethu Ramesh
DSN
2000
IEEE
14 years 27 days ago
Resource Scheduling in Dependable Integrated Modular Avionics
In the recent development of avionics systems, Integrated Modular Avionics (IMA) is advocated for next generation architecture that needs integration of mixedcriticality real-time...
Yann-Hang Lee, Daeyoung Kim, Mohamed F. Younis, Je...
RV
2010
Springer
220views Hardware» more  RV 2010»
13 years 6 months ago
Runtime Verification with the RV System
The RV system is the first system to merge the benefits of Runtime Monitoring with Predictive Analysis. The Runtime Monitoring portion of RV is based on the successful Monitoring O...
Patrick O'Neil Meredith, Grigore Rosu