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» Formal Analysis of Processor Timing Models
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ICS
2001
Tsinghua U.
14 years 27 days ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
KDD
2007
ACM
165views Data Mining» more  KDD 2007»
14 years 8 months ago
Efficient and effective explanation of change in hierarchical summaries
Dimension attributes in data warehouses are typically hierarchical (e.g., geographic locations in sales data, URLs in Web traffic logs). OLAP tools are used to summarize the measu...
Deepak Agarwal, Dhiman Barman, Dimitrios Gunopulos...
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
14 years 26 days ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
GROUP
2009
ACM
14 years 2 months ago
Lazy scheduling of processing and transmission tasks in collaborative systems
A collaborative system must perform both processing and transmission tasks. We present a policy for scheduling these tasks on a single core that is inspired by studies of human pe...
Sasa Junuzovic, Prasun Dewan
ICNP
2005
IEEE
14 years 2 months ago
On Understanding of Transient Interdomain Routing Failures
The convergence time of the interdomain routing protocol, BGP, can last as long as 30 minutes [14,15]. Yet, routing behavior during BGP route convergence is poorly understood. BGP...
Feng Wang, Lixin Gao, Jia Wang, Jian Qiu