Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor

Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., implicit threads) from the sequential execution stream and speculatively executes them in parallel on multiple processor cores. These proposals augment a conventional multiprocessor, which employs explicit threading, with the ability to handle implicit threads. Current proposals focus on only implicitly-threaded code sections. This paper identifies, for the first time, the issues in combining explicit and implicit threading. We present the Multiplex architecture to combine the two threading models. Multiplex exploits the similarities between implicit and explicit threading, and provides a unified support for the two threading models without additional hardware. Multiplex groups a subset of protocol states in an implicitlythreaded CMP to provide a write-invalidate protocol for explicit threads. Using a fully-i...

• Type: Conference
• Year: 2001
• Where: ICS
• Authors: Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar
• Keywords: Distributed And Parallel Computing, Explicit Threading, ICS 2001, Implicit Threads, Threading Models