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» Formal Analysis of Processor Timing Models
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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 2 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
13 years 12 months ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
CASES
2004
ACM
14 years 1 months ago
Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations
Many optimization techniques, including several targeted specifically at embedded systems, depend on the ability to calculate the number of elements that satisfy certain conditio...
Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vi...
BMCBI
2008
218views more  BMCBI 2008»
13 years 8 months ago
LOSITAN: A workbench to detect molecular adaptation based on a Fst-outlier method
Background: Testing for selection is becoming one of the most important steps in the analysis of multilocus population genetics data sets. Existing applications are difficult to u...
Tiago Antao, Ana Lopes, Ricardo J. Lopes, Albano B...
DAC
2005
ACM
14 years 9 months ago
Energy optimal speed control of devices with discrete speed sets
We obtain analytically, the energy optimal speed profile of a generic multi-speed device with a discrete set of speeds, to execute a given task within a given time. Current implem...
Ravishankar Rao, Sarma B. K. Vrudhula