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HYBRID
2010
Springer
14 years 15 days ago
Safe compositional network sketches: formal framework
NetSketch is a tool for the specification of constrained-flow applications and the certification of desirable safety properties imposed thereon. NetSketch assists system integr...
Azer Bestavros, Assaf J. Kfoury, Andrei Lapets, Mi...
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
14 years 2 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
FMICS
2008
Springer
13 years 9 months ago
Formal Verification of the Implementability of Timing Requirements
There has been relatively little work on the implementability of timing requirements. We have previously provided definitions of fundamental timing operators that explicitly consid...
Xiayong Hu, Mark Lawford, Alan Wassyng
FMCAD
2006
Springer
13 years 11 months ago
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
Pervasive Logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include init...
Tilman Glökler, Jason Baumgartner, Devi Shanm...
P2P
2006
IEEE
14 years 1 months ago
Cost-Based Analysis of Hierarchical DHT Design
Flat DHT architectures have been the main focus of the research on DHT design so far. However, there have been also a number of works proposing hierarchical DHT organizations and ...
Stefan Zöls, Zoran Despotovic, Wolfgang Kelle...