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TACAS
1998
Springer
14 years 21 days ago
1998
Springer
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
BIRTHDAY
2003
Springer
14 years 1 months ago
2003
Springer
One of the central axioms of extreme programming is the disciplined use of regression testing during stepwise software development. Due to recent progress in software model checkin...
RE
2001
Springer
14 years 28 days ago
2001
Springer
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
IFIP
2007
Springer
14 years 2 months ago
2007
Springer
Many large-scale Internet applications optimize their overlay network to reduce latencies. Embedding coordinate systems like Vivaldi are valuable tools for this new range of applic...