77 search results - page 12 / 16 » Formal Property Verification by Abstraction Refinement with ... |
SAC
2009
ACM
14 years 2 months ago
2009
ACM
Formalization is a necessary precondition for the specification of precise and unambiguous use case models, which serve as reference points for the design and implementation of so...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
We introduce a generic extension of the popular branching-time logic CTL which refines the temporal until and release operators with formal languages. For instance, a language may ...
FMCAD
2004
Springer
13 years 11 months ago
2004
Springer
Abstract. We present a simple method for verifying the safety properties of cache coherence protocols with arbitrarily many nodes. Our presentation begins with two examples. The fi...
CDC
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract-- We propose a formal method for feedback controller synthesis using interactive computer programs with graphical interface (in short, computer games). The main theoretica...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...