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» Formal Reliability Analysis Using Theorem Proving
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ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
14 years 1 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
SYNTHESE
2010
87views more  SYNTHESE 2010»
13 years 7 months ago
Proofs, pictures, and Euclid
Though pictures are often used to present mathematical arguments, they are not typically thought to be an acceptable means for presenting mathematical arguments rigorously. With re...
John Mumma
QEST
2009
IEEE
14 years 3 months ago
Recent Extensions to Traviando
—Traviando is a trace analyzer and visualizer for simulation traces of discrete event dynamic systems. In this paper, we briefly outline recent extensions of Traviando towards a...
Peter Kemper
ICSE
2009
IEEE-ACM
14 years 9 months ago
Analyzing critical process models through behavior model synthesis
Process models capture tasks performed by agents together with their control flow. Building and analyzing such models is important but difficult in certain areas such as safety-cr...
Christophe Damas, Bernard Lambeau, Francois Roucou...
FMCAD
2007
Springer
14 years 3 months ago
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC
—When model-checking reports that a property holds on a model, vacuity detection increases user confidence in this result by checking that the property is satisfied in the inte...
Jocelyn Simmonds, Jessica Davies, Arie Gurfinkel, ...