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DAC
1996
ACM
14 years 18 days ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
UML
2001
Springer
14 years 26 days ago
A Formal Mapping between UML Static Models and Algebraic Specifications
: There are several reasons to specify UML models in a formal way The most important are to avoid inconsistencies and ambiguities and to do verification and forecasting of system p...
Liliana Favre
FAC
2000
114views more  FAC 2000»
13 years 8 months ago
Representational Reasoning and Verification
Formal approaches to the design of interactive systems rely on reasoning about properties of the t a very high level of abstraction. Specifications to support such an approach typi...
Gavin J. Doherty, José Creissac Campos, Mic...
COMPSEC
2010
142views more  COMPSEC 2010»
13 years 5 months ago
Provably correct Java implementations of Spi Calculus security protocols specifications
Spi Calculus is an untyped high level modeling language for security protocols, used for formal protocols specification and verification. In this paper, a type system for the Spi ...
Alfredo Pironti, Riccardo Sisto
SAM
2004
98views Hardware» more  SAM 2004»
13 years 9 months ago
Scenario Synthesis from Imprecise Requirements
Discovering faults in requirements specifications for distributed reactive systems is a challenging problem since many issues that need to be uncovered are a result of subtle compo...
Bill Mitchell, Robert Thomson, Paul Bristow