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RE
2001
Springer
14 years 28 days ago
Virtual Environment Modeling for Requirements Validation of High Consequence Systems
An essential type of “evidence”of the correctness of the requirements formalization process can be provided by human-based calculation. Human calculation can be significantly ...
Victor L. Winter, Dejan Desovski, Bojan Cukic
SAC
2010
ACM
13 years 6 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
14 years 7 days ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella
CADE
2010
Springer
13 years 9 months ago
Multi-Prover Verification of Floating-Point Programs
Abstract. In the context of deductive program verification, supporting floatingpoint computations is tricky. We propose an expressive language to formally specify behavioral proper...
Ali Ayad, Claude Marché
DSVIS
1998
Springer
14 years 21 days ago
A Uniform Approach for Specification and Design of Interactive Systems: the B Method
: We have experienced the B Method on a case study which was defined by the French working group on formalisms for interactive systems, i.e. a Post-It
Yamine Aït Ameur, Patrick Girard, Francis Jam...