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» Formal Verification of Cognitive Models
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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
14 years 17 days ago
A process algebra interpretation of a verification oriented overlanguage of VHDL
The VOVHDL language was defined as a verification oriented VHDL
Catherine Bayol, Bernard Soulas, Dominique Borrion...
CHI
2004
ACM
14 years 8 months ago
A constraint satisfaction approach to predicting skilled interactive cognition
In this paper we report a new approach to generating predictions about skilled interactive cognition. The approach, which we call Cognitive Constraint Modeling, takes as input a d...
Alonso H. Vera, Andrew Howes, Michael McCurdy, Ric...
WETICE
2005
IEEE
14 years 2 months ago
Application of Lightweight Formal Methods to Software Security
Formal specification and verification of security has proven a challenging task. There is no single method that has proven feasible. Instead, an integrated approach which combines...
David P. Gilliam, John D. Powell, Matt Bishop
NJC
2006
88views more  NJC 2006»
13 years 8 months ago
Optimizing Slicing of Formal Specifications by Deductive Verification
Slicing is a technique for extracting parts of programs or specifications with respect to certain criteria of interest. The extraction is carried out in such a way that properties ...
Ingo Brückner, Björn Metzler, Heike Wehr...
HYBRID
1998
Springer
14 years 20 days ago
Formal Verification of Safety-Critical Hybrid Systems
This paper investigates how formal techniques can be used for the analysis and verification of hybrid systems [1,5,7,16] -- systems involving both discrete and continuous behavior....
Carolos Livadas, Nancy A. Lynch