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» Formal Verification of Cognitive Models
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CONCUR
2006
Springer
14 years 6 days ago
Sanity Checks in Formal Verification
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
Orna Kupferman
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
13 years 10 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
FORTE
1994
13 years 9 months ago
An improvement in formal verification
Critical safety and liveness properties of a concurrent system can often be proven with the help of a reachability analysis of a finite state model. This type of analysis is usual...
Gerard J. Holzmann, Doron Peled
PERCOM
2010
ACM
13 years 6 months ago
Towards automated verification of autonomous networks: A case study in self-configuration
In autonomic networks, the self-configuration of network entities is one of the most desirable properties. In this paper, we show how formal verification techniques can verify the ...
JaeSeung Song, Tiejun Ma, Peter R. Pietzuch
FMICS
2010
Springer
13 years 9 months ago
SMT-Based Formal Verification of a TTEthernet Synchronization Function
Abstract. TTEthernet is a communication infrastructure for mixedcriticality systems that integrates dataflow from applications with different criticality levels on a single network...
Wilfried Steiner, Bruno Dutertre