ISQED 2010 - PDF Preprint Papers

ISQED 2010 International Symposium on Quality Electronic Design

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ISQED
2010
IEEE

227views Hardware» more ISQED 2010»

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks

14 years 6 months ago

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Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...

Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...

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Id	Views	Title	Status

1	227	Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks	claim
2	194	Accelerating trace computation in post-silicon debug	claim
3	177	Multi-corner, energy-delay optimized, NBTI-aware flip-flop design	claim
4	176	A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead	claim
5	170	New SRAM design using body bias technique for ultra low power applications	claim
6	161	Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint	claim
7	156	On the design of different concurrent EDC schemes for S-Box and GF(p)	claim
8	151	Leakage temperature dependency modeling in system level analysis	claim
9	141	Assessing chip-level impact of double patterning lithography	claim
10	137	Automated silicon debug data analysis techniques for a hardware data acquisition environment	claim
11	137	Analysis of power supply induced jitter in actively de-skewed multi-core systems	claim
12	135	Signal probability control for relieving NBTI in SRAM cells	claim
13	133	UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications	claim
14	128	Soft error rate determination for nanoscale sequential logic	claim
15	128	A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur	claim
16	127	Limits of bias based assist methods in nano-scale 6T SRAM	claim
17	126	Modeling and verification of industrial flash memories	claim
18	123	Yield-constrained digital circuit sizing via sequential geometric programming	claim
19	121	A novel two-dimensional scan-control scheme for test-cost reduction	claim
20	120	Methodology from chaos in IC implementation	claim
21	117	Variation-aware speed binning of multi-core processors	claim
22	114	Toward effective utilization of timing exceptions in design optimization	claim
23	105	Leakage current analysis for intra-chip wireless interconnects	claim
24	103	Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor	claim

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