67 search results - page 10 / 14 » Formal Verification of Digital Circuits Using Symbolic Terna... |
158
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SIGSOFT
2007
ACM
16 years 4 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
151
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CIIA
2009
15 years 5 months ago
2009
Abstract. Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration (mainly model checking and equivalence checking) or deduct...
133
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CORR
2010
Springer
15 years 4 months ago
2010
Springer
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
149
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FMICS
2006
Springer
15 years 7 months ago
2006
Springer
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
168
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DAC
2010
ACM
15 years 7 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...