67 search results - page 4 / 14 » Formal Verification of Digital Circuits Using Symbolic Terna... |
FORMATS
2004
Springer
13 years 11 months ago
2004
Springer
We discuss the modeling and verification of real-time systems using the SAL model checker. A new modeling framework based on event calendars enables dense timed systems to be descr...
JSA
2008
13 years 7 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...
EUROMICRO
2000
IEEE
14 years 4 days ago
2000
IEEE
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...