67 search results - page 7 / 14 » Formal Verification of Digital Circuits Using Symbolic Terna... |
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. This paper presents a scalable method for parallel symbolic on-the-fly model checking in a distributed memory environment. Our method combines a scheme for on-the-fly mod...
EURODAC
1994
IEEE
13 years 12 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Abstract-- Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based ...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
CORR
2010
Springer
13 years 6 months ago
2010
Springer
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and ...