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» Formal Verification of Digital Systems
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QEST
2010
IEEE
15 years 2 months ago
DTMC Model Checking by SCC Reduction
Discrete-Time Markov Chains (DTMCs) are a widely-used formalism to model probabilistic systems. On the one hand, available tools like PRISM or MRMC offer efficient model checking a...
Erika Ábrahám, Nils Jansen, Ralf Wim...
RE
2001
Springer
15 years 8 months ago
Events and Constraints: A Graphical Editor for Capturing Logic Requirements of Programs
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
Margaret H. Smith, Gerard J. Holzmann, Kousha Etes...
DATE
2005
IEEE
102views Hardware» more  DATE 2005»
15 years 10 months ago
Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator
The idea of design domain specific Mother Model of IP block family as a base of modeling of system integration is presented here. A common reconfigurable Mother Model for ten diff...
Hannu Heusala, Jussi Liedes
ECMDAFA
2006
Springer
166views Hardware» more  ECMDAFA 2006»
15 years 8 months ago
Dynamic Logic Semantics for UML Consistency
Abstract. The Unified Modelling Language (UML) is intended to describe systems, but it is not clear what systems satisfy a given collection of UML diagrams. Stephen Mellor has desc...
Greg O'Keefe
SIGSOFT
2005
ACM
16 years 5 months ago
Fluent temporal logic for discrete-time event-based models
Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-b...
Emmanuel Letier, Jeff Kramer, Jeff Magee, Sebasti&...