Sciweavers

176 search results - page 16 / 36
» Formal Verification of Gate-Level Computer Systems
Sort
View
WSC
1998
13 years 9 months ago
Validation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing
Simulation modeling provides an effective and powerful approach for capturing and analyzing complex manufacturing systems. More and more decisions are based on computer generated ...
Nirupama Nayani, Mansooreh Mollaghasemi
IPPS
1999
IEEE
13 years 12 months ago
Mechanical Verification of a Garbage Collector
Abstract. We describe how the PVS verification system has been used to verify a safety property of a garbage collection algorithm, originally suggested by Ben-Ari. The safety prope...
Klaus Havelund
ESORICS
2010
Springer
13 years 8 months ago
Verifying Security Property of Peer-to-Peer Systems Using CSP
Due to their nature, Peer-to-Peer (P2P) systems are subject to a wide range of security issues. In this paper, we focus on a specific security property, called the root authenticit...
Tien Tuan Anh Dinh, Mark Ryan
EDOC
2000
IEEE
13 years 12 months ago
Model Checking of Workflow Schemas
Practical experience indicates that the definition of realworld workflow applications is a complex and error-prone process. Existing workflow management systems provide the means,...
Christos T. Karamanolis, Dimitra Giannakopoulou, J...
ICSE
2007
IEEE-ACM
14 years 7 months ago
Plug-and-Play Architectural Design and Verification
Abstract. In software architecture, components represent the computational units of a system and connectors represent the interactions among those units. Making decisions about the...
Shangzhu Wang, George S. Avrunin, Lori A. Clarke