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» Formal Verification of Gate-Level Computer Systems
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ASM
2008
ASM
13 years 10 months ago
Model Checking Event-B by Encoding into Alloy
As systems become ever more complex, verification becomes more main stream. Event-B and Alloy are two formal specification languages based on fairly different methodologies. While...
Paulo J. Matos, João Marques-Silva
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 17 days ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
PODC
2011
ACM
12 years 11 months ago
Securing social networks
We present a cryptographic framework to achieve access control, privacy of social relations, secrecy of resources, and anonymity of users in social networks. The main idea is to u...
Michael Backes, Matteo Maffei, Kim Pecina
JAR
2008
81views more  JAR 2008»
13 years 8 months ago
Automatic Symmetry Detection for Promela
We introduce a specification language, Promela-Lite, which captures the essential features of Promela but which, unlike Promela, has a formally defined semantics. We show how we ca...
Alastair F. Donaldson, Alice Miller
ASPDAC
2005
ACM
99views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Implication of assertion graphs in GSTE
- We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu S...