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» Formal Verification of Gate-Level Computer Systems
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ARTS
1999
Springer
13 years 12 months ago
ProbVerus: Probabilistic Symbolic Model Checking
Model checking can tell us whether a system is correct; probabilistic model checking can also tell us whether a system is timely and reliable. Moreover, probabilistic model checkin...
Vicky Hartonas-Garmhausen, Sérgio Vale Agui...
RSP
2006
IEEE
125views Control Systems» more  RSP 2006»
14 years 1 months ago
Creation and Validation of Embedded Assertion Statecharts
This paper addresses the need to integrate formal assertions into the modeling, implementation, and testing of statechart based designs. The paper describes an iterative process f...
Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Dem...
SAC
2006
ACM
13 years 7 months ago
Transformation of yEPC business process models to YAWL
Model transformations are frequently applied in business process modeling to bridge between languages on a different abstraction and formality. In this paper, we define a transfor...
Jan Mendling, Michael Moser, Gustaf Neumann
TCBB
2008
137views more  TCBB 2008»
13 years 7 months ago
Toward Verified Biological Models
The last several decades have witnessed a vast accumulation of biological data and data analysis. Many of these data sets represent only a small fraction of the system's behav...
Avital Sadot, Jasmin Fisher, Dan Barak, Yishai Adm...
MAGS
2008
169views more  MAGS 2008»
13 years 7 months ago
ACVisualizer: A visualization tool for APi-calculus
Process calculi are mathematical tools used for modeling and analyzing the structure and behavior of reactive systems. One such calculus, called APi-calculus (an extension to Pi-ca...
Raheel Ahmad, Shahram Rahimi