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» Formal Verification of Gate-Level Computer Systems
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ICNP
1999
IEEE
13 years 11 months ago
Automated Protocol Implementations Based on Activity Threads
In this paper we present a new approach for the automated mapping of formal descriptions into activity thread implementations. Our approach resolves semantic conflicts by reorderi...
Peter Langendörfer, Hartmut König
26
Voted
VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
14 years 8 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...
PAMI
2002
136views more  PAMI 2002»
13 years 7 months ago
On the Individuality of Fingerprints
Fingerprint identification is based on two basic premises: (i) persistence: the basic characteristics of fingerprints do not change with time; and (ii) individuality: the fingerpr...
Sharath Pankanti, Salil Prabhakar, Anil K. Jain
ICFP
2006
ACM
14 years 7 months ago
Static typing for a faulty lambda calculus
A transient hardware fault occurs when an energetic particle strikes a transistor, causing it to change state. These faults do not cause permanent damage, but may result in incorr...
David Walker, Lester W. Mackey, Jay Ligatti, Georg...
IPPS
2010
IEEE
13 years 4 months ago
Runtime checking of serializability in software transactional memory
Abstract--Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these ...
Arnab Sinha, Sharad Malik