216 search results - page 1 / 44 » Formal Verification of Safety Properties in Timed Circuits |
ASYNC
2000
IEEE
13 years 11 months ago
2000
IEEE
ENTCS
2006
13 years 6 months ago
2006
The application of formal methods to analog and mixed signal circuits requires efficient methods tructing abstractions of circuit behaviors. This paper concerns the verification o...
HYBRID
2007
Springer
13 years 10 months ago
2007
Springer
Abstract. In this paper, we propose a new approach for formal verification of hybrid systems. To do so, we present a new refinement proof technique, a weak refinement using step in...
ISQED
2003
IEEE
14 years 2 days ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
FMCAD
2000
Springer
13 years 10 months ago
2000
Springer
We take a fresh look at the problem of how to check safety properties of finite state machines. We are particularly interested in checking safety properties with the help of a SAT-...