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» Formal Verification of Safety Properties in Timed Circuits
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ENTCS
2006
109views more  ENTCS 2006»
13 years 7 months ago
Incremental Verification for On-the-Fly Controller Synthesis
The CIRCA system automatically synthesizes hard real-time discrete event controllers from plant and environment descriptions. CIRCA's automatically-synthesized controllers pr...
David J. Musliner, Michael J. S. Pelican, Robert P...
COMCOM
2000
97views more  COMCOM 2000»
13 years 7 months ago
Verification of security protocols using LOTOS-method and application
We explain how the formal language LOTOS can be used to specify security protocols and cryptographic operations. We describe how security properties can be modelled as safety prop...
Guy Leduc, François Germeau
DFG
2004
Springer
13 years 11 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...
FM
2008
Springer
171views Formal Methods» more  FM 2008»
13 years 9 months ago
Assume-Guarantee Verification for Interface Automata
Interface automata provide a formalism capturing the high level interactions between software components. Checking compatibility, and other safety properties, in an automata-based ...
Michael Emmi, Dimitra Giannakopoulou, Corina S. Pa...
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler