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» Formal Verification of Safety Properties in Timed Circuits
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ISSE
2007
13 years 7 months ago
Specifying real-time properties in autonomic systems
Increasingly, computer software must adapt dynamically to changing conditions. The correctness of adaptation cannot be rigorously addressed without precisely specifying the require...
Ji Zhang, Zhinan Zhou, Betty H. C. Cheng, Philip K...
ICWE
2005
Springer
14 years 1 months ago
The Role of Visual Tools in a Web Application Design and Verification Framework: A Visual Notation for LTL Formulae
As the Web becomes a platform for implementing complex B2C and B2B applications, there is a need to extend Web conceptual modeling to process-centric applications. In this context,...
Marco Brambilla, Alin Deutsch, Liying Sui, Victor ...
ICECCS
1998
IEEE
161views Hardware» more  ICECCS 1998»
13 years 12 months ago
A Method and a Technique to Model and Ensure Timeliness in Safety Critical Real-Time Systems
The main focus of this paper is the problem of ensuring timeliness in safety critical systems. First, we introduce a method and its associated technique to model both real-time ta...
Christophe Aussaguès, Vincent David
ISARCS
2010
156views Hardware» more  ISARCS 2010»
13 years 9 months ago
A Road to a Formally Verified General-Purpose Operating System
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
Martin Decký
SACMAT
2009
ACM
14 years 2 months ago
Towards formal security analysis of GTRBAC using timed automata
An access control system is often viewed as a state transition system. Given a set of access control policies, a general safety requirement in such a system is to determine whethe...
Samrat Mondal, Shamik Sural, Vijayalakshmi Atluri