216 search results - page 20 / 44 » Formal Verification of Safety Properties in Timed Circuits |
FM
2003
Springer
14 years 23 days ago
2003
Springer
We present a semantics for fault tree analysis, a technique used for the analysis of safety critical systems, in the real-time interval logic Duration Calculus with Liveness and sh...
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
FDL
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
IJIT
2004
13 years 9 months ago
2004
As computer network technology becomes increasingly complex, it becomes necessary to place greater requirements on the validity of developing standards and the resulting technology...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...