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» Formal Verification of Safety Properties in Timed Circuits
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DATE
2009
IEEE
90views Hardware» more  DATE 2009»
14 years 2 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
EDOC
2000
IEEE
13 years 12 months ago
Model Checking of Workflow Schemas
Practical experience indicates that the definition of realworld workflow applications is a complex and error-prone process. Existing workflow management systems provide the means,...
Christos T. Karamanolis, Dimitra Giannakopoulou, J...
FORMATS
2009
Springer
14 years 2 months ago
Analyzing Real-Time Event-Driven Programs
Embedded real-time systems are typically programmed in low-level languages which provide support for event-driven task processing and real-time interrupts. We show that the model c...
Pierre Ganty, Rupak Majumdar
ICTAC
2004
Springer
14 years 28 days ago
Real Time Reactive Programming in Lucid Enriched with Contexts
Abstract. We present a synchronous approach to real-time reactive programming in Lucid enriched with contexts as first class objects. The declarative intensional approach allows r...
Kaiyu Wan, Vasu S. Alagar, Joey Paquet
WWW
2005
ACM
14 years 8 months ago
Design for verification for asynchronously communicating Web services
We present a design for verification approach to developing reliable web services. We focus on composite web services which consist of asynchronously communicating peers. Our goal...
Aysu Betin-Can, Tevfik Bultan, Xiang Fu