216 search results - page 32 / 44 » Formal Verification of Safety Properties in Timed Circuits |
ENTCS
2002
13 years 7 months ago
2002
The MaC system has been developed to provide assurance that a target program is running correctly with respect to formal requirements specification. This is achieved by monitoring...
HASE
2007
IEEE
13 years 11 months ago
2007
IEEE
In current model-based development practice, validation that we are building a correct model is achieved by manually deriving requirements-based test cases for model testing. Mode...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
POPL
2005
ACM
14 years 7 months ago
2005
ACM
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
B
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. A recent contribution to the formal specification and verification of concurrent systems is the integration of the state- and event-based approaches B and CSP, specifical...