216 search results - page 34 / 44 » Formal Verification of Safety Properties in Timed Circuits |
FORMATS
2004
Springer
14 years 27 days ago
2004
Springer
We propose an effective and complete method for verifying safety and properties of timed systems, which is based on predicate abstraction for g finite abstractions of timed autom...
RTAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Distributed hard real-time systems require guaranteed communication. One common approach is to restrict network access by enforcing a time-division multiple access (TDMA) schedule...
SASN
2003
ACM
14 years 22 days ago
2003
ACM
The purpose of this work is to automate the analysis of ad hoc routing protocols in the presence of attackers. To this end, a formal model of protocol behavior is developed in whi...
DAC
2010
ACM
13 years 10 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
SIGSOFT
2003
ACM
14 years 8 months ago
2003
ACM
This paper describes a compositional proof strategy for verifying properties of requirements specifications. The proof strategy, which may be applied using either a model checker ...