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» Formal Verification of Safety Properties in Timed Circuits
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ICFP
2004
ACM
14 years 8 months ago
Verification of safety properties for concurrent assembly code
Concurrency, as a useful feature of many modern programming languages and systems, is generally hard to reason about. Although existing work has explored the verification of concu...
Dachuan Yu, Zhong Shao
FMCAD
2000
Springer
14 years 6 days ago
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
David A. Basin, Stefan Friedrich, Sebastian Mö...
HYBRID
1998
Springer
14 years 25 days ago
Formal Verification of Safety-Critical Hybrid Systems
This paper investigates how formal techniques can be used for the analysis and verification of hybrid systems [1,5,7,16] -- systems involving both discrete and continuous behavior....
Carolos Livadas, Nancy A. Lynch
DATE
2002
IEEE
108views Hardware» more  DATE 2002»
14 years 1 months ago
A Case Study for the Verification of Complex Timed Circuits: IPCMOS
ions + Assume Guarantee + Induction GOAL: Formal verification of the IPCMOS architecture
Marco A. Peña, Jordi Cortadella, Alexander ...
FSTTCS
2000
Springer
14 years 6 days ago
Formal Verification of the Ricart-Agrawala Algorithm
Abstract. This paper presents the first formal verification of the RicartAgrawala algorithm [RA81] for distributed mutual exclusion of an arbitrary number of nodes. It uses the Tem...
Ekaterina Sedletsky, Amir Pnueli, Mordechai Ben-Ar...