216 search results - page 5 / 44 » Formal Verification of Safety Properties in Timed Circuits |
TII
2008
13 years 8 months ago
2008
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...
ITC
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
FOSSACS
2008
Springer
13 years 10 months ago
2008
Springer
Whereas formal verification of timed systems has become a very active field of research, the idealised mathematical semantics of timed automata cannot be faithfully implemented. Se...
ICSE
2008
IEEE-ACM
14 years 8 months ago
2008
IEEE-ACM
This paper examines the suitability and use of runtime verification as means for monitoring security protocols and their properties. In particular, we employ the runtime verificat...
SAFECOMP
2007
Springer
14 years 2 months ago
2007
Springer
A strategy and relating activities of a software safety analysis (SSA) are presented for the software of a digital reactor protection system where software modules in the design de...