216 search results - page 6 / 44 » Formal Verification of Safety Properties in Timed Circuits |
FORMATS
2006
Springer
14 years 14 days ago
2006
Springer
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
FTCS
1998
13 years 10 months ago
1998
Ensuring the correctness of computer systems used in lifecritical applications is very difficult. The most commonly used verification methods, simulation and testing, are not exha...
FMICS
2008
Springer
13 years 10 months ago
2008
Springer
Given the intractability of exhaustively verifying software, the use of runtime-verification, to verify single execution paths at runtime, is becoming popular. Although the use of ...
CAV
2007
Springer
14 years 3 months ago
2007
Springer
In this paper we propose a complete chain for synthesizing controllers from high-level specifications. From real-time properties expressed in the logic MTL we generate, under boun...
ENTCS
2006
13 years 8 months ago
2006
Patterns for property specification enable non-experts to write formal specifications that can be used for automatic model checking. The existing patterns identified in [6] allow ...