216 search results - page 7 / 44 » Formal Verification of Safety Properties in Timed Circuits |
FMCAD
2008
Springer
13 years 9 months ago
2008
Springer
We present a general approach for verifying safety properties of Lustre programs automatically. Key aspects of the approach are the choice of an expressive first-order logic in wh...
CODES
2008
IEEE
13 years 9 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
FORTE
1994
13 years 9 months ago
1994
Critical safety and liveness properties of a concurrent system can often be proven with the help of a reachability analysis of a finite state model. This type of analysis is usual...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...