216 search results - page 8 / 44 » Formal Verification of Safety Properties in Timed Circuits |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
BIRTHDAY
2007
Springer
13 years 11 months ago
2007
Springer
We present a verification methodology for cooperating traffic agents covering analysis of cooperation strategies, realization of strategies through control, and implementation of c...
CAV
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...
ISOLA
2007
Springer
14 years 1 months ago
2007
Springer
We present a model of the IEEE 1394 Root Contention Protocol with a proof of Safety. This model has real-time properties which are expressed in the language of the event B method: ...
FORMATS
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. Introducing a monitor on a system typically changes the system's behaviour by slowing the system down and increasing memory consumption. This may possibly result in ...