216 search results - page 9 / 44 » Formal Verification of Safety Properties in Timed Circuits |
DATE
2004
IEEE
2004
IEEE
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
13 years 11 months ago
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
POPL
2009
ACM
14 years 8 months ago
2009
ACM
We present a unified approach to type checking and property checking for low-level code. Type checking for low-level code is challenging because type safety often depends on compl...
STTT
2010
13 years 2 months ago
2010
We present a model of the IEEE 1394 Root Contention Protocol with a proof of Safety. This model has real-time properties which are expressed in the language of the event B method: ...
EPK
2006
13 years 9 months ago
2006
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
FTRTFT
1992
Springer
13 years 11 months ago
1992
Springer
Real-Time Logic is a formal notation for reasoning about temporal behaviour. Z is a general purpose specification language, but lacks explicit features for expressing real-time co...